This invention relates to a memory device. In addition, the invention relates to a method of forming a corresponding memory device. Semiconductor memory devices include arrays of memory cells that are arranged in rows and columns. The gate electrodes of rows of memory cell transistors are connected by word lines, by which the memory cells are addressed. The word lines usually are formed by patterning a conductive layer stack so as to form single word lines which are arranged in parallel. The word lines are electrically insulated from one another laterally by a dielectric material. The lateral distance between two word lines and the width of a word line sum to the pitch of the array of word lines. The pitch is the dimension of the periodicity of a periodic pattern arrangement. The word lines succeed one another in a completely periodic fashion, in order to reduce the necessary device area as much as possible. Likewise, the bit lines are formed by patterning a conductive layer so as to form the single bit lines which are electrically insulated from one another by a dielectric material.
An example of a non-volatile memory device is based on the NROM (nitride read-only memory) technology. FIG. 1A illustrates a cross-sectional view of an NROM cell between I and I as is illustrated in FIG. 1B. In one embodiment, the NROM cell is an n-channel MOSFET device, wherein the gate dielectric is replaced with a storage layer stack 46. As is illustrated in FIG. 1A, the storage layer stack 46 is disposed above the channel 43 and under the gate electrode 44. The storage layer stack 46 includes a silicon nitride layer 202, which stores the charge, and two insulating silicon dioxide layers 201, 203, which sandwich the silicon nitride layer 202. The silicon dioxide layers 201, 203 have a thickness larger than 5 nm to avoid any direct tunnelling. In the NROM cell illustrated in FIG. 1A two charges are stored at each of the edges adjacent to the n source/drain regions 41, 42.
The NROM cell is programmed by channel hot electron injection (CHE), for example, whereas erasing is accomplished by hot hole enhanced tunnelling (HHET), by applying appropriate voltages to the corresponding bit lines and word lines, respectively.
FIG. 1B illustrates a plan view of an exemplary memory device including an array 100 of a NROM cells. To be more specific, the memory cell array 100 includes word lines 2 extending in a first direction as well as bit lines extending in a second direction. Memory cells 45 are disposed between adjacent bit lines at each point of intersection of a substrate portion with a corresponding word line 2. The first and second source/drain regions 41, 42 form part of corresponding bit lines. The gate electrodes 44 form part of a corresponding word line. At a point of intersection of the word lines and bit lines, the bit lines and the word lines are insulated from each other by a thick silicon dioxide layer (not shown). In order to minimize the area required for the memory cell array 100, it is desirable to reduce the width of the word lines as much as possible. Nevertheless, for contacting the single word lines landing pads 111 having a minimum area are required. Usually, these landing pads 111 are disposed in a fan-out region 110 adjacent to the memory cell array 100. In order to achieve a contact having an appropriate contact resistance, the area of each of the landing pads 111 must have a minimum value. In the peripheral portion 120, the transistors for controlling the action of the memory cell array are disposed. In one embodiment, word line drivers, sense amplifiers and other transistors are disposed in the peripheral portion 120. Usually, the peripheral portion 120 is formed in the CMOS technology. Due to the special programming method for injecting a charge into the memory cells, the transistors disposed in the peripheral portion 120 have to withstand higher voltages than the transistors disposed in the array portion. As a consequence, the channel length of the corresponding transistors in the peripheral portion amount to approximately 0.5 μm and higher. In one embodiment, this channel length cannot be reduced in order to achieve a reduced area of the peripheral portion 120 and, thus, the memory device.
As is illustrated in FIG. 1B, the word lines 2 have a minimum width wmin and a minimum distance dmin from each other. In order to increase the package density of such a memory cell array, the width and the distance of the word lines could be reduced. However, a reduced width of the word lines will result in an increased sheet resistance resulting in an increased access time and, thus, causing an inferior device performance. In addition, when shrinking the width of the word lines 2, a minimum contact area in the fan-out region 110 should be maintained. Alternatively, it is possible to further shrink the distance between adjacent word lines. However, if the word line array is patterned by using a photolithography technique that is usually employed, the lateral dimensions of the word lines as well as the distance between neighbouring word lines is limited by the minimal structural feature size which is obtainable by the technology used. A special problem arises if the landing pads and the array of conductive lines are to be patterned by one single lithographic step. In more detail, the area of the landing pads should be large, whereas the distance of the conductive lines should be small. However, a lithographic step for simultaneously image different ground rules is very difficult to implement. Hence, a patterning method is sought by which it is possible to simultaneously pattern structures having a different ground rule.